Then one could fairly assume (though it's not always the case!) that the datasheet had been examined.

Now, just what is it about DRAM, SDRAM, etc, that you don't see as random-access? It's true that synchronous DRAM is most generally used in bursts, mainly because the CPU has internal cache that needs loaded, but they can be randomly accessed. It's just faster to do it in bursts, so, when paired with a sizeable cache, it's likely to yield better performance to move data to/from it in bursts.

Back when we used plated-wire memory, cores, etc, those memories were random access enough, but core, for example required a special command in order to ensure the data wasn't damaged when read.

In some architectures, in order to speed up access to the relatively slow (1.2-1.5 microsecond) core memory, there were specific (read-only) memory commands, that were required when reading data that had to be refreshed in order to preserve it. A scratchpad often didn't require that. "Register" (they didn't have 'em, back then, values were stored in scratchpad. Rather than call and return using a stack, they used JST (jump and store) instructions, where the action was to load the address bus with the target address, store the PC at the target location and begin executing instructions after that location. When the subroutine ended it would jump to the return address stored at its beginning. That address certainly didn't have to be preserved.

RE