Quoting from the Atmel AT89LP8052 data sheet Section 7.3:

The RST pin of the AT89LP51/52 can function as either an active-low reset input or as an active high
reset input. The polarity of the RST pin is selectable using the POL pin (formerly EA). When
POL is high the RST pin is active high with an on-chip pull-down resistor tied to GND. When
POL is low the RST pin is active low with an on-chip pull-up resistor tied to VDD. The RST pin
structure is shown in Figure 7-3. In Compatibility mode the reset pin is sampled every six clock
cycles and must be held active for at least twelve clock cycles to trigger the internal reset. In
Fast mode the reset pin is sampled every clock cycle and must be held active for at least two
clock cycles to trigger the internal reset.

Michael Karas