Yes, all traces have capacitances.

Which is the reason why software/hardware should make sure that produced signals have enough settle times so a data signal has time to stabilize after having charged/discharged the capacitance, before the data is latched.

And the reason why the data signal must have enough hold time, so the clock signal has time to deactivate before the data signal is removed.

All lines have capacitances, and the goal is to try to minimize this capacitance.

It is not a good idea to add extra capacitance to slow down one signal, just because another signal already is too slow. Any slow down should be handled by the software or by hardware configuration settings.

When adding a memory module to a PC, the end user shouldn't try different load capacitors to try to adjust the clocking. Instead, the memory controller sets number of clock cycles to delay each individual step of the memory accesses, based on the speed of the installed memory module.

We don't solve too sweet coffee by adding salt, even if it does make the coffee taste less sweet. We shouldn't try to solve missing settle or hold times with extra capacitances even if it does look like it works. A chip manufacturer who releases hardware that can't produce reasonable timing should be shot, since the only alternative that produces correct signals is a bit-banged solution.

Capacitances doesn't just delay a signal. It delays the signal by slowing down the flanks. And in some situations, these slower flanks may result in other problems, unless the inputs have enough hysterese. So besides getting a signal that is time-delayed, a circuit may become seriously affected by noisy environments.