You didn't share what chip types and how they are interconnected to produce the 2-wire interface via SCL and SDA lines. Maybe with more info like that we could suggest something.

One reason I do not recommend the capacitor solution is that this increases the rise and fall times of SDA and SCL signals. With little or no actual designed in hold time you get even more uncertainty where the real logic thresholds of Clock versus Data actually occur and you can end up making your hold time look even worse than without the capacitors!!

If you are using an MCU with an 2-wire interface that has an onboard peripheral controller then you should look for an MCU that claims SMBus compatibility. To meet SMBus specifications the design has to ensure 300 nsec hold time on SDA after SCL falls to low level. Note the 2-Wire peripheral on SiLabs parts such as the C8051F344 are SMBus compatible and the SDA setup and hold time actually can be adjusted to allow for a larger number of system clocks of setup/hold time when the SYSCLK is running at higher rates.

If you are bit banging the interface then adjusting the time relationship between SCL and SDA is a matter of re-working the bitbang code.

Michael Karas