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???
12/11/10 00:58
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 		 #180072 - Just a thought....
Responding to: ???'s previous message
Every article and datasheet involving I2C I have looked at always shows the positive SCL pulse clearly in the center of the SDA pulse with any changes in SDA occuring after SCL has gone low and before it goes high. The scope image you have shown shows SDA transitions during SCL transitions. Could this possibly cause inadvertent STOP and START conditions during bit transfers? With the monitor attached the bus characteristics may have changed sufficiently to prevent the race conditions when both signals change nearly at the same time.

List of 36 messages in thread
TopicAuthorDate
Aaargh, it only works with the monitor connected            01/01/70 00:00      
   Scope            01/01/70 00:00      
      No obvious difference            01/01/70 00:00      
         May not help            01/01/70 00:00      
         Just a thought....            01/01/70 00:00      
   ground            01/01/70 00:00      
      Setup and hold            01/01/70 00:00      
         0ns hold is allowed indeed...            01/01/70 00:00      
            Bus Speed?            01/01/70 00:00      
               Reply to all            01/01/70 00:00      
                  Add capacitance :-|(            01/01/70 00:00      
                     Other options?            01/01/70 00:00      
                        Chip Types and Connections            01/01/70 00:00      
                           chip type            01/01/70 00:00      
                           ADuC7026 and 24LC16            01/01/70 00:00      
                              If serial EEPROM not in critical path...            01/01/70 00:00      
                                 Another thing...            01/01/70 00:00      
                                    that is ridiculous!!!            01/01/70 00:00      
                                       I know...            01/01/70 00:00      
                                       Ridiculous - but not unique, I'm afraid            01/01/70 00:00      
                                          Fully licensed interface            01/01/70 00:00      
                                             Stop Timing?            01/01/70 00:00      
                                                If I could figure out how            01/01/70 00:00      
                     Resolved? 39pF added to SDA            01/01/70 00:00      
                        NOw..ok            01/01/70 00:00      
                           Chewing gum            01/01/70 00:00      
                              Agreed            01/01/70 00:00      
                           Where?            01/01/70 00:00      
                        points            01/01/70 00:00      
                           "Features of a 51"...            01/01/70 00:00      
         do You have            01/01/70 00:00      
         to long track of SDA and SCL            01/01/70 00:00      
            huh?            01/01/70 00:00      
               the cable also            01/01/70 00:00      
                  re: the cab;e            01/01/70 00:00      
                     Capacitance slows flanks - but slow flanks needs hysterese            01/01/70 00:00      

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