but with its weaknesses fixed. That would require a ~25-35 ns access time, and 24 mA outputs available at each I/O pin. The obvious improvement is inherent in the elimination of the need for external buffers to drive real-world loads, and the capability of running with fast MCU's without extensive pain
In this discussion, when I suggest improvements, you push "but it should be a drop-in" now you talk about "elimination of the need for external buffers" who would care about that for a "drop-in replacement". AGAIN if it is a drop in, forget it, those that use the 8255 are slowpoking anyhow, if it is not, make a much better chip, do not get mired in the old mud.

This means that the part can operate at 100 MHz, yet generate an external bus cycle at nominally 5 MHz, which is sufficient for the fastest 8255's
this is CRAZY
1) some f12x have 8 ports, why even think of killing 3 to get an antique 3 porter on the board
2) if you have external data memory (and thus do not kill 3 ports) you have two unpleasant options a) the overhead of constanly changing external bus speed or b) accessing external data at slowpoke speed.
re a) seems easy, but consider interrupt overhead (when the int hits, you need to save 'mode' set the mode the ISR need do your stuff and then restore 'mode')

Erik