First of all, the MCU's nRD and nWR are only of interest if there's an external memory bus.

The absence of nRD does not imply an undefined state, though the time lag between nCS and nRD and nWR does exist.

Since nRD merely steers the data bus buffers, aside from clearing some functional flipflops, it's valid to deduce that signal from the absence of nWR. Motorola did this with their series of peripheral chips, since their microprocessors lacked a distinct read signal.

If there's no external bus, which would be rare in the replacement market, it would be practical to drive nRD and nWR from the MCU, which, for new applications, would be quite valid. However, the original device would not function properly without the concurrence of nRD and nCS. In order to save the one pin, one could INTERNALLY gate nCS with nWR and deduce from the absence of nWR, that nRD was implied. This would probably be a minimal change in the logic. If nWR (internally) were used to generate an internal nRD, the device would be able to proceed in more or less the same way as it presently does, though the bus timing would have to change in order to accomodate the time window between nCS and nWR. The nWR alone can steer the data bus buffers. nCS can imply the output enable. The part that gets dicey is the way in which status flipflops are managed. That would be a challenge for the redesign. It would, of course, be a redesign, and that implies all the "usual" risks. I've never believed this would be an ideal solution. It is, however, possible to implement. Externally generated nCS, from the occurrence of either nRD or nWR, would be better, as in effectively grounding nCS, but it wouldn't work as a replacement. If one wished to do this with a CPLD, that's essentially ruled out in a PLCC44 because they haven't enough I/O's. It's possible to do the job with a larger part, but, of course, it's no longer a replacement.

CPLD's, BTW, have no internal tristates. They make up for this by means of large multiplexers that are easily constructed in their shared logic arrays. The logic is defined in macrocells, with a substantial bit of logic at its inputs and having an association with an output pin, unlike FPGA logic cells, which are much more limited due to their relatively small lookup tables. CPLD's can support the same sort of logic that would otherwise demand tristate routing paths in an FPGA by means of large input multiplexers at the inputs. The effect is the same.

RE