but with its weaknesses fixed. That would require a ~25-35 ns access time, and 24 mA outputs available at each I/O pin. The obvious improvement is inherent in the elimination of the need for external buffers to drive real-world loads, and the capability of running with fast MCU's without extensive pain.

I took another look at those SiLabs 100 MIPS MCU's that you like, and noted that the do, in fact, have the ability to provide an external memory bus, and have SFR's suitable for extending the length of the bus cycle in three portions, namely the setup time before nRD and nWR, the width of nWR and nRD, and the address hold time after nRD and nWR. This means that the part can operate at 100 MHz, yet generate an external bus cycle at nominally 5 MHz, which is sufficient for the fastest 8255's. The device seems to be capable of operating from a demultiplexed bus, thereby improving performance of the external bus.

Likewise, the Maxim/Dallas DS89C4x0 has similar options.

If an 8255 with sufficient output current, and a 75-90 ns access time, as Lynn suggested, the "new" 8255 would be suitable for quite a few applications. Yes, you'd have to give up the two or three ports on the MCU in order to interface the 8255, but you'd have some higher current outputs than what the MCU offers. If you wanted a second 8255 or a third, or a fourth, you'd lose no more ports.

RE