| ??? 11/02/06 10:42 Read: times |
#127249 - on using undefined states Responding to: ???'s previous message |
Richard Erlacher said:
The logic can decode the absence of nWR in the presence of nCS in order to generate the nRD signal, regardless of what its purpose is. This creates new timing restrictions, of course, but it's doable. The deduced nRD is still capable of doing what the externally applied one would do. I'm afraid this requires a certain style of how the 8255 is connected. Mind, one could simply ground the /CS and mask the /RD and /WR from processor with the decoded address range of 8255. Hence, it is not legitimate to output data on the data bus in absence of /RD just because /CS is active, as this might result in collision with other devices on the bus. Not to mention, that changing "meaning" of the /RD pin means it is not a fully backward compatible drop-in replacement. My suggestion would be to use the same approach of using "previously undefined states" but in slightly different style: if both high-to-low and low-to-high going transition of /CS occurs consecutively without any activity of /RD or /WR, on the latter /CS transition I would latch-in the "extra" configuration word. Also, I see an undefined behaviour on both /RD and /WR active in the Intersil datasheet, this state could be used for the extra write signal, but it is a very tricky approach (similar approach was used in the then AY-3-8910/12; but when we tried to simulate it in programmable logic we found out it is very hard to distinguish all the three "active" states...) A third option might be to use a 3-state input logic, which is not (but the process used might prohibit this): high, low and middle (= floating). /CS might be sampled for this at the moment when /RD or /WR goes active, and if in the "floating" state, the alternative functions apply. All these have their pitfalls, too, I admit... Jan Waclawek Richard Erlacher said:
...some of this is vastly inflated by the marketing departments of FPGA makers, who tell you that a 3-input gate is really three two-input gates, while some people realize that it's really just two extra emitters added to a single transistor. Well, I don't think the FPGAs use the same technology as the 7400 used some 40 years ago... :-) |
