| ??? 05/02/10 14:33 Modified: 05/02/10 14:34 Read: times |
#175603 - 4 -> 10 nsec Pulse Does Not Work for MCU Responding to: ???'s previous message |
Joe:
In his first posting Arun stated that he is using the AT89S52 MCU. When using the external interrupt inputs on an 8051 variant type part one has to obey certain timing requirements on the input pin to get the interrupt to be recognized. Timing requirements will vary from vendor to vendor and will change based upon clock frequency and clock divider ratio. The following taken from the "8051 bible" should help explain the requirements. Note that many MCU data sheets fail to point out or discuss this at all. 8051 Bible says said:
External Interrupts
The external sources can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt. Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the external source has to hold the request pin high for at least one cycle, and then hold it low for at least one cycle. This is done to ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically cleared by the CPU when the service routine is called. If the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. So based on that your "generic dual edge detection" will not work for an MCU that uses sampled edge detection. I also fully agree with Jez that the design approach you describe is problematic. It may work in your lab but fail to work correctly in some cases out in the field. You could modify your design some so that it would be a little better by changing the two inverters to 74xx14 type parts and then putting a series R in the signal path between the two. Then add some C to ground at the input of the second inverter. Proper selection of R and C would extends the resulting pulse width out to a length that would make it be not so dependent on voltage, chip characteristics and the phase of the moon. The method described by Kiran is the tried and true method of providing a dual edge interrupt capability. That method has a significant advantage in that the MCU software can at all times know what edge has caused the interrupt. In many pulse train detection algorithms this is essential information. In one application that I worked on where Kiran idea was used it was necessary in the decoding algorithm so sometimes detect on rising edge only and then sometimes on both edges. Some newer variant types have dual edge interrupt capability built in. This can eliminate the need for the external XOR gate. If these are used for pulse train detection the software may need to be able to read the interrupt signal in the ISR to be able determine which edge caused the interrupt. One needs to make sure your specific MCU allows the interrupt signal to be directly read this way. The XOR approach with the external gate does not need to be able to read the interrupt signal because the port pin that comes out from the MCU will tell you which level caused the current interrupt. Michael Karas |
