The uC in question has a reset pin that works like this. Problem is: The reset controller uses aforementioned slow clock for things like sampling the reset pin and timing the reset pulse on power-on.
The uC in question has already beed declared defective since a simple one bit can stop the WD, thus the discussion has turnd into a general WD discussion, please read my post in that light.

Erik Malund said:if a total reset does not 'clear' your system, how can a power cycle?

If a reset does not return the processor to the same state that a power cycles would, then only a power cycle will truly "reset" the system.
a) I was talking about the whole circuit, not just the uC
b) a WD reset, that is not "full" is worthless. I will allow exceptions for thing (e.g. RAM) than on power cycle are random, not being so after a WD reset.

if the processor does not do b) throw it out

Erik