The problem here would be that after being zapped with enough ESD to flip that one bit that switches from internal RC to external crystal or clock, the processor is in no state to perform that clock test anymore. (Yes, being zapped with lots of ESD is part of our application, and while it's fine for the device to cease working while being zapped, it's not acceptable to keep playing dead after the zapping has stopped)

Oh, yeah, and the reset controller runs off said slow clock, too. Even if you could detect a loss of the slow clock, the reset controller would be stopped, too. Or it would start to reset and hang as soon as it tries to use the slow clock (for timing the power-on reset pulse or similar), since switching back to internal RC as the clock source requires a power cycle, not just a reset.