| ??? 02/21/12 11:16 Modified: 02/21/12 11:26 Read: times |
#186094 - It's a feature, actually. Responding to: ???'s previous message |
Oliver Sedlacek said:
The killer bug that you seem to have uncovered is that you need to power cycle your chip rather than just giving it a reset. Actually, it's a feature (and well documented in the datasheet). It makes sense if you need a highly accurate slow clock (*) and cannot accept that the chip runs off the internal RC oscillator (which has generous tolerances) for even a few clock cycles, even when it's being reset. Flip the bit once, and the chip will stay on the external clock until you turn off power (**). The problem only occurs if you don't need the external slow clock and expect the chip to stay on its internal RC oscillator. (*) The chips real-time timer runs off the slow clock too, and the internal "32 kHz" RC oscillator is actually specified to 20...44 kHz. Not good at all if you expect the chip to count second accurately. (**) However, I wonder if ESD or similar could then flip the bit that switches between external crystal oscillator and external clock signal - both would be connected to the same pins, and having a clock signal while the chip expects a crystal oscillator would probably mess up the slow clock, too. |
