The uC in question has a reset pin that works like this. Problem is: The reset controller uses aforementioned slow clock for things like sampling the reset pin and timing the reset pulse on power-on.

Without a slow clock, the processor will never recognize an external reset, and it will become stuck after an internal reset (since it tries to run on the unavailable slow clock which can only be returned to internal RC by cycling power).

Also, there's a number of states (boundary scan, fast flash programming mode) in which the processor will not respond to a reset and required a power cycle to return to regular operation.



If a reset does not return the processor to the same state that a power cycles would, then only a power cycle will truly "reset" the system.