Jack's article is an interesting read. I've certainly been vexed by the problem that a WDT must generate a chip reset to be any good, but how do you find out what happened. In the past I've used the NMI option to capture the processor state in EEPROM, which took some doing. I really like the Silabs design that generates an ISR 128 cycles before asserting the chip reset, but other designs could work. Some processors have a "reset reason" register, so you can tell whether the WDT kicked in. It would be nice if the WDT assertion captured the processor state to provide some debug breadcrumbs.