This circuit is attempt to store non-repetative
fast signal (thanks , Erik Malund) - with parts , which are available on market and can be soldered with hand.
It uses "massive parallelism" (thanks, Jan Waclawek).
And this circuit (only sampler) goes far away from
"small money"- maybe 400USD.


Sampler contains ten (10) miniboards , each with one ADC+FIFO.
These boards are attashed to main board
with analog front-end ,clock and control logic.

Miniboard and some logic is drawn in
"http://www.8052.com/users/stefan63/my2d.gif".
Clock distribution is shown in
"http://www.8052.com/users/stefan63/my1d.gif".

Main parts are:
ADC - MAX1198-100MHz
http://datasheets.maxim-ic.com/en/ds/MAX1198.pdf
FIFO - SN74V245 - 6ns cycle.
http://www.ti.com/lit/gpn/sn74v245
delay lines - 3D3424-1.
http://www.datadelay.com/datasheets/3d3424.pdf
This delay line i didnt find in online store.

.
Maximum clock will be 100MHz. With delay lines
at this clock 10 boards will perform 10 samples in 10ns .
Before triggering FIFO will be "empty" - writing WCLK and reading RCLK clocks are enabled WEN' and REN'signals will be enabled (write enable WEN',read enable REN').
When triggering occurs- signal REN'will be disabled trough
flip-flop D2. FIFO will be filled with data until
PAF'goes active (active low - "programmable allmost full flag"").
This signal will disable WEN' trough flip-flop D1 (PAF'must be iverted').

Controller will see WEN'is high and can read FIFO -
providing low speed read clock trough D3 - multiplexer and
REN' trough D2.

When all data is read WEN'must to be released to low trough D1 -
to start new sampling cicle. REN'must be reset to low too.

Clock distribution utilises delay lines with inherent delay about
9ns , delay step abut 1 ns, 16 steps (9..24 ns delay)


Any critics and sugestions are welcome.
This is not device to be build today or tomorrow, this is something like excercise.
regards,
Stefan