I'm partial to the Spartan-II types because they're 5-volt tolerant. That makes it easy to use them in combination with the 805x's, whether 3-volt or 5-volt.

These parts DO have tristate resources internal to the die, though other families may not. The Altera FPGA's, AFAIK, and I haven't recently kept up, do not. They generally convert tristate demands into multiplexers in software. In some cases, most, in fact, there are heavy penalties for using more than one LUT in a given function, whether it's a long counter or a multiplexer. Any logic function that won't fit within a single LUT will be slowed down by the routing/cascading delay associated with concatenation of multiple LUT's. This is generally quite well documented, as are the techniques recommended for minimizing this penalty.

CPLD's have no such penalty unless the required multiplexer is very wide. Most CPLD's have wide enough gates that you can easily decode a single 16-bit address with no cascading penalty at all. What's more, the timing in a CPLD is deterministic, as is the pinout. You seldom have to sacrifice timing for pin assignments or vice-versa. I've found that I can do a lot in a XC95108 that I have difficulty doing with an FPGA costing 6x as much.

FPGA's are, typically, logic-poor and register-rich, while CPLD's are register-poor. You'd have no difficulty in using every register in a CPLD, however, where getting to 60% utilization in an FPGA is a challenge, and doubly so if timing is a concern.

RE