| ??? 02/24/07 04:12 Read: times |
#133618 - But in the 8254 datasheet, Responding to: ???'s previous message |
Yes. i got your points to some extent Lynn.
so you mean to say there should not be any tri-state logic in a design. only two states., logic '1' & logic '0'. is it so? But in the 8254 datasheet, the input 8 bit data bus of timer is a tri-state bidirectional buffer. how it could be achieved since you said about the tristate problem? i did the below code for designing a 8 bit tristate bidirectional bus to communicate with the counters of 8254 assign data_io = ((!cs && !rd)?ctr_dout:8'bZZZZZZZZ); assign ctr_din = ((!cs && !wr)?data_io:8'bZZZZZZZZ); should i change it to two states., so that the code becomes, assign data_io = ((!cs && !rd)?ctr_dout:8'b00000000); assign ctr_din = ((!cs && !wr)?data_io:8'b00000000); regard's Suresh. |
| Topic | Author | Date |
| Simulation and Synthesis of verilog code | 01/01/70 00:00 | |
| my comments on having a quick look | 01/01/70 00:00 | |
| if..else... | 01/01/70 00:00 | |
| Changes to verilog code | 01/01/70 00:00 | |
| worst case?? | 01/01/70 00:00 | |
| Logical "Z" state, data buses, and more | 01/01/70 00:00 | |
| Not sure what happens in verilog but vhdl | 01/01/70 00:00 | |
Verilog vs VHDL types | 01/01/70 00:00 | |
| But in the 8254 datasheet, | 01/01/70 00:00 | |
| More on Verilog data buses | 01/01/70 00:00 | |
| Thank you Lynn! | 01/01/70 00:00 | |
| XILILNX is the problem! | 01/01/70 00:00 | |
| Spartan II is just out of choices | 01/01/70 00:00 | |
| There are good reasons for Spartan-II | 01/01/70 00:00 | |
| Altera is doubly unhelpful | 01/01/70 00:00 | |
| Where's the 805x? | 01/01/70 00:00 | |
| well, he is fooling with a 8254 | 01/01/70 00:00 | |
| "chat forum" | 01/01/70 00:00 | |
| Well, OK ... | 01/01/70 00:00 | |
| how was I to know that? | 01/01/70 00:00 | |
| mentioned in an earlier thread Erik., | 01/01/70 00:00 |