it s certainly faster than a standard 8254.Looking at your code having chains of if..... else's in hardware terms at least causes the compiler to produce very deeply nested multiplexors so that can cause the whole design to be slow,also if... then ...else implies proirity.The standard solution in VHDL at any rate is to use case statements which don't imply any priority
case control_expression is

when test_expression1 =>
statements
when test_expression2 =>
statements
when others =>
statements

end case;

although not being a verilog person i am not sure of the correct incantation in verilog.
also as far as i understand it your always@ is using CS as a clock input but there is no sensitivity list and I have no way of knowing if the other inputs are syncronous with cs.I would be vary wary of using cs in that way and then having some conditional logic dependant of other signals which may or maynot be syncronous.