| ??? 02/23/07 17:52 Read: times |
#133577 - worst case?? Responding to: ???'s previous message |
Lynn Reed said:
In real life, z signals always float to the exact state that you don't want. In the best case, you draw power. In the worst case, you may enable two different registers on an internal data bus, causing a conflict, and possibly destroying the chip.
Since "ctr0_wr" is tri state in my code., refering to your description, i think the best case is logic '1' which i would be using. what do you mean by worst case in tristate? and how it enables two different registers on an internal bus? i would like to have some information on it Lynn. regard's Suresh. |
| Topic | Author | Date |
| Simulation and Synthesis of verilog code | 01/01/70 00:00 | |
| my comments on having a quick look | 01/01/70 00:00 | |
| if..else... | 01/01/70 00:00 | |
| Changes to verilog code | 01/01/70 00:00 | |
| worst case?? | 01/01/70 00:00 | |
| Logical "Z" state, data buses, and more | 01/01/70 00:00 | |
| Not sure what happens in verilog but vhdl | 01/01/70 00:00 | |
Verilog vs VHDL types | 01/01/70 00:00 | |
| But in the 8254 datasheet, | 01/01/70 00:00 | |
| More on Verilog data buses | 01/01/70 00:00 | |
| Thank you Lynn! | 01/01/70 00:00 | |
| XILILNX is the problem! | 01/01/70 00:00 | |
| Spartan II is just out of choices | 01/01/70 00:00 | |
| There are good reasons for Spartan-II | 01/01/70 00:00 | |
| Altera is doubly unhelpful | 01/01/70 00:00 | |
| Where's the 805x? | 01/01/70 00:00 | |
| well, he is fooling with a 8254 | 01/01/70 00:00 | |
| "chat forum" | 01/01/70 00:00 | |
| Well, OK ... | 01/01/70 00:00 | |
| how was I to know that? | 01/01/70 00:00 | |
| mentioned in an earlier thread Erik., | 01/01/70 00:00 |