| ??? 02/23/07 19:20 Read: times Msg Score: +1 +1 Good Answer/Helpful |
#133581 - Not sure what happens in verilog but vhdl Responding to: ???'s previous message |
There are in fact two fundamental data types the unresolved types std_ulogic and the resolved types std_logic.
With the unresolved types it is illegal for there to be two values simultaniously driven onto a ulogic signal so you can use the unresolved type to catch errors such as overlapping tristate signals.Thats the theory anyway sadly almost nobody bothers with ulogic in practice. but there are basically nine different signal levels defined 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care With resolved types you can drive them with multiple signals and use what are called resolution functions to determine the outcome. |
| Topic | Author | Date |
| Simulation and Synthesis of verilog code | 01/01/70 00:00 | |
| my comments on having a quick look | 01/01/70 00:00 | |
| if..else... | 01/01/70 00:00 | |
| Changes to verilog code | 01/01/70 00:00 | |
| worst case?? | 01/01/70 00:00 | |
| Logical "Z" state, data buses, and more | 01/01/70 00:00 | |
| Not sure what happens in verilog but vhdl | 01/01/70 00:00 | |
Verilog vs VHDL types | 01/01/70 00:00 | |
| But in the 8254 datasheet, | 01/01/70 00:00 | |
| More on Verilog data buses | 01/01/70 00:00 | |
| Thank you Lynn! | 01/01/70 00:00 | |
| XILILNX is the problem! | 01/01/70 00:00 | |
| Spartan II is just out of choices | 01/01/70 00:00 | |
| There are good reasons for Spartan-II | 01/01/70 00:00 | |
| Altera is doubly unhelpful | 01/01/70 00:00 | |
| Where's the 805x? | 01/01/70 00:00 | |
| well, he is fooling with a 8254 | 01/01/70 00:00 | |
| "chat forum" | 01/01/70 00:00 | |
| Well, OK ... | 01/01/70 00:00 | |
| how was I to know that? | 01/01/70 00:00 | |
| mentioned in an earlier thread Erik., | 01/01/70 00:00 |