| ??? 02/23/07 17:01 Read: times |
#133569 - if..else... Responding to: ???'s previous message |
Jez Smith said:
Looking at your code having chains of if..... else's in hardware terms at least causes the compiler to produce very deeply nested multiplexors so that can cause the whole design to be slow,
oh. i have implemented the entire design using if..esle statements. i did like this just because i could able to achieve the entire funtionality of 8254 by this way at first try. any way.. i could make it better if i could achive the entire funtionality first. regard's Suresh. |
| Topic | Author | Date |
| Simulation and Synthesis of verilog code | 01/01/70 00:00 | |
| my comments on having a quick look | 01/01/70 00:00 | |
| if..else... | 01/01/70 00:00 | |
| Changes to verilog code | 01/01/70 00:00 | |
| worst case?? | 01/01/70 00:00 | |
| Logical "Z" state, data buses, and more | 01/01/70 00:00 | |
| Not sure what happens in verilog but vhdl | 01/01/70 00:00 | |
Verilog vs VHDL types | 01/01/70 00:00 | |
| But in the 8254 datasheet, | 01/01/70 00:00 | |
| More on Verilog data buses | 01/01/70 00:00 | |
| Thank you Lynn! | 01/01/70 00:00 | |
| XILILNX is the problem! | 01/01/70 00:00 | |
| Spartan II is just out of choices | 01/01/70 00:00 | |
| There are good reasons for Spartan-II | 01/01/70 00:00 | |
| Altera is doubly unhelpful | 01/01/70 00:00 | |
| Where's the 805x? | 01/01/70 00:00 | |
| well, he is fooling with a 8254 | 01/01/70 00:00 | |
| "chat forum" | 01/01/70 00:00 | |
| Well, OK ... | 01/01/70 00:00 | |
| how was I to know that? | 01/01/70 00:00 | |
| mentioned in an earlier thread Erik., | 01/01/70 00:00 |