As a general rule, tri-state buses are only used between chips. Inside of a chip (ASIC or FPGA) it is better not to use "Z" state signals.

Your output data bus can be a mux with the last state being Z

data_out = ctl0_rd ? reg0 :
           ctl1_rd ? reg1 :
           ctl2_rd ? reg2 : 8'bz;

but everybody else needs to be defined at all times.

If you have a tristatable bus, that implies that multiple signals can be gated onto it. That also implies the possibility of two different signals being gated on the bus at the same time. As a designer, you must insure that NEVER happens.

If you specify a control signal as Z, then it will be either a 0 or a 1. You will not know which it is. Remember, there is no such thing as a z in real life.

So, if ctl0_rd is a 1, and ctl1_rd is a 1, and ctl2_rd is a 1, then what happens? It depends on your synthesizer. It could be that you will have a bus conflict, which will draw current. Perhaps enough current to burn out internal wires. Just for reference, many internal routing signals use metal lines with a maximum current rating of ~100uA.

Finally, if your internal data bus floats to a 2.5v level, it may cause the logic connected to it to draw large amounts of current which can also damage the chip. Another rule is that if you must have an internal data bus, then it should never float. Someone must be gated onto it at all times.