| ??? 12/22/06 06:33 Read: times |
#129968 - What did you really test? Responding to: ???'s previous message |
Lynn Reed said:
From a DC point of view, I was interested in determining the characteristics of the output transistors on all of the pins.
I programmed the part so that all outputs were low (Mode 0, all outputs written to with a "0", then read "0"'s from port a on the data bus. The tester then forced 0.4v on each pin, one at a time, and measured the current necessary to do so. I didn't try to look for Vol differences between pins due to IR drops along the internal busses. It is easy enough to do, but that just characterizes the Intersil internal power busses. I repeated this with all outputs programmed to a "1", and forcing Vdd - 0.4V on each pin. As I said, you lost me here, as I don't see the relevance of measuring so small a voltage change on a digital circuit that normally switches between +5 and GND. According the the OKI specification (I've got the Intersil spec, but not where I can find it <sigh>), it should source no LESS than 3.7 volts into a load that sinks 2.5 mA. How does your measurement technique relate in any way to verifying that? From where I sit, you should be sourcing current from your output into a load that sinks 2.5 mA and you should see at least that 3.7 volts. As you increase the load, because, as you've said, the sourcing FET looks like a resistor, as the current increases, it should drop more millivolts, so you can simply increase the current in the sink (load) until the voltage drops to 3.7. Only there will you have the information you need. Likewise, as I described before, you need to find how HIGH the output goes when you drive a positive current source. Measuring a high with a high makes no sense. Measuring a low with a low doesn't either. -------- For AC timing, I wrote a 1 MHz vector that exercised all pins. I then ran a Shmoo plot varying the output strobe timing on 1 axis, and Vdd on the other. The slowest path produces a failure, which is recorded on the plot. For my purposes, I know how transistor performance varies with temperature and voltage. I don't know the particulars of the processing of the particular chip I was measuring, though I could find out if I was interested. These days, fab processing is very consistent, and unlikely to vary over the full specified range. -------- We haven't fully decided whether or not to make the 8255. If we do, then access times are going to be on the order of <25ns, and the output strengths will be somewhere between 16 and 24 mA. The pinout has only one ground, and that poses a problem for high current drive. There are tricks I can do to prevent transients from affecting the design, but that only moves the problem from internal to external. I am inclined to use powerful outputs with slew rate control to minimize transients, and provide a maximum total Iol limitation. That lets the customer choose where they want to sink the current. I don't know which pins on the DIP-40 you'd sacrifice. I agree that you can use a couple of the unused PLCC pins for GND and a couple for Vdd. That always helps, I suppose. As for the spec, what I need to know is (a) how long a nCS to nRD and nWR setup is required, (b) how long a data-valid to rising-edge of nWR is required, (c) how long a data-valid hold time from rising-edge of nWR is required, how long from falling-edge of nRD to data-out-valid, and how long data is valid after the rising edge of nRD. Aside from that, precise spec's regarding the handshaking and interrupt signals on port C with respect to port A and B transactions would be useful. If you can build 'em such that they drive a 100-ohm load to either rail, that would be good, but 150 ohms would probably be adequate. If the thing has to be buffered in order to drive those loads, it's easier simply to use family logic to produce the required I/O function, as common 8-bit-wide parts can drive those loads. RE |
