| ??? 12/21/06 20:18 Read: times |
#129950 - What I Did Responding to: ???'s previous message |
Richard says:
Just what DID you do? -------- From a DC point of view, I was interested in determining the characteristics of the output transistors on all of the pins. I programmed the part so that all outputs were low (Mode 0, all outputs written to with a "0", then read "0"'s from port a on the data bus. The tester then forced 0.4v on each pin, one at a time, and measured the current necessary to do so. I didn't try to look for Vol differences between pins due to IR drops along the internal busses. It is easy enough to do, but that just characterizes the Intersil internal power busses. I repeated this with all outputs programmed to a "1", and forcing Vdd - 0.4V on each pin. -------- For AC timing, I wrote a 1 MHz vector that exercised all pins. I then ran a Shmoo plot varying the output strobe timing on 1 axis, and Vdd on the other. The slowest path produces a failure, which is recorded on the plot. For my purposes, I know how transistor performance varies with temperature and voltage. I don't know the particulars of the processing of the particular chip I was measuring, though I could find out if I was interested. These days, fab processing is very consistent, and unlikely to vary over the full specified range. -------- We haven't fully decided whether or not to make the 8255. If we do, then access times are going to be on the order of <25ns, and the output strengths will be somewhere between 16 and 24 mA. The pinout has only one ground, and that poses a problem for high current drive. There are tricks I can do to prevent transients from affecting the design, but that only moves the problem from internal to external. I am inclined to use powerful outputs with slew rate control to minimize transients, and provide a maximum total Iol limitation. That lets the customer choose where they want to sink the current. |
