Routing an escape path for each of 1148 pins (balls) on a fpPBGA (fine-pitch plastic ball grid array) will require 6 or 8 layers anyway, particularly if the pitch is 0.5 mm or 0.8 mm. Fewer, perhaps, if blind and buried vias are used. Once one is in multilayer boards, however, the incremental cost of manufacture is not so bad going from 6 to 8 or thereabouts. Testing, with fpPBGA's is always a hassle. Specific provision for testing connectivity between critical paths needs to be designed into the board so that JTAG or other automated testing can be implemented.

Adding a few layers, since these devices seem to want their core supply (~1.2V) and at least one I/O supply(2.5 or 3.3V), and the external peripherals will want whatever they want (1.5, 1.8, 2.5, 3.3, or 5.0 volts), supply layers make the board easier and all-around better for supply distribution. Sometimes a dedicated GND layer for part of the circuit is better than sharing the common. This is not always the case, however.

The examples I've seen have routed the GND connections to the annulus on the inside of the fpPBGA, where bypass members can be connected easily, thereby relieving the congestion that often occurs when all the bypass is attached close to the outside.

Escape routing from 1148 pins is no picnic! The signals are of no use, though, if you can't get them to where they're needed.

RE