From the two very different examples I tend to say that the concrete cap values are rather irrelevant. I know, you want to build something beautiful, but I think the layout considerations are more important than the exact cap values. Or by other words, with an unsuited layout you can damage more than you gain by a sophisticated choice of cap values.

I, personally, would use identical caps (not mentioning the huge caps), 100nF in 0402 package for instance, in combination with a layout which uses as shortest and widest copper traces with as many vias as possible. The use of a mulitlayer board is the crucial point in such an application, of course!

By the way: Figure 8 of this application note

http://www.xilinx.com/bvdocs/appnotes/xapp623.pdf

is no more than a joke! Reality looks totally different! What figure 8 shows is what they hope to get, an impedance curve showing a very low impedance, free of any unsane maxima. In reality you get something totally different, something that is nearly unpredicatble! What these people forget is, that you cannot put some hundreds of caps on a board without resulting in additional copper trace inductivities between them, which are hugely bigger than the SMD package inductivities and which makes this wonderful theoretical impedance calculation entirely invalid! Not even mentioning these annoying bond wires' inductivities internally of chip...

Kai