It's absolutely the case that the newer 805x-core MCU's have more features, and, perhaps, considerably less in common with the original pre-1980 parts. However, despite the fact that those early parts lacked the internal supervoltage-generating charge pumps required for FLASH writing/erasing, the fact that those early parts could corrupt BBRAM in a manner and under circumstances similar to the ones under which FLASH corruption occurs, i.e. during Vdd decay with active RESET, persuades me that there's still a common issue, perhaps associated with the relationship, as the datasheet to which you refer, wherein the relationship between RESET and the Vdd level becomes dangerous.

I believe that you, Kai, once pointed out that there might have been oscillator startup issues that required the long-time-constant in the RESET circuit that Intel originally recommended. That time constant is very much longer than the >24 oscillator cycles that were the specified minimum length RESET pulse width. If that long RESET is required to ensure that the oscillator is stabile, and perhaps also that whatever internal processes that are kept secret can be ensured complete, then someone should have told us. Nevertheless, I find it unpleasant that on not-so-rare occasion, the MCU runs on during active RESET, once the Vdd is well below specified limits, but still high enough to cause problems, and perhaps still exceed the minima specified for other in-system (such as the BBRAM with which I first encountered this anomaly).

The circumstance to which I refer is, of course, a specific one, but since the problem to which I refer occurs with components of vintage ranging from 2002 (as in the Maxim/Dallas DS89C420) back to the 1980-marked Intel 8751H, also including parts from Siemens, Philips, and AMD, I believe it's something that, at least as recently as a decade ago, persisted in many of the common variants. However, I suspect that whatever causes this specific failure mode is still intrinsic to the chip design, and must therefor be dealt with. The fact that I observed this in a circuit with a supervisor IC suggests to me that the run-on problem occurs during decay of Vdd and not during power-up. For that reason, it's likely that it could occur during any brownout condition.

I'm still anxious to find some sort of specification that actually sets a minimum on safe rise and fall of the positive supply to 805x-core MCU's. I still don't see this as being directly addressed in any specification, aside, perhaps, from the early Intel specification. That one, however, doesn't say anything about the decay. It's safe minimal limits on the rise and fall of Vdd that I'm seeking, however, and not just recommendations. I know that I can exercise the IC through a million cycles with no ill effect, and then, on the next cycle, have a problem. Without a manufacturer's specification, we're all on our own.

RE