Kai,

I haven't run into much information about the MCU behavior during rise/fall time of Vcc. While I agree that there are many things going on during rise and fall of Vcc, there should, in fact, be nothing externally observable happening during Vcc rise and fall if RESET is asserted, aside from oscillator startup during Vcc rise. Nevertheless, I've observed external signals, as mentioned previously, during the decay of Vcc to levels below the specified minimum after external power is cut off. As I've never completed my investigation into this matter, I'm still persuaded that something needs to be done to inhibit internal processes during active RESET.

From what I've observed, there are two critical timespans, one during power-up, which is less critical, and one during Vcc decay during shutdown, when internal processes, including the flash-write supervoltage charge pump, may still be running.

All these problems are addressable, albeit not so inexpensively. I suspect that they may be manageable with a small CPLD, which probably won't cost more than the larger supervisors, but certainly will impact cost more than the 3-terminal types, particularly in a system with a small, low-cost MCU.

One of these days, soon, I hope, I'll get back to this matter. I've never set up a complete test environment for it, and just the setup will take a couple of weeks, I suppose. Design of the mechanism to control the respective timing of RESET and Vcc rise and fall will take considerable time and effort. Presently, I'm persuaded that a very short rise-time, but one long enough to allow reliable oscillator startup is essential, and that a very short cutoff of Vcc, down to very nearly 0 Volts, is essential to stop the processes that, under presently common circumstances, continue while Vcc is decaying, where supervisors do little other than to assert RESET once Vcc is below tolerable levels, is what is needed.

If you can provide a link to a datasheet or other document that specifies details of Vcc rise and fall, I would be very grateful.

RE