Two aren't 805x-core and the NXP unit is quite different in that is uses a low-going reset signal. If Intel had used a low-going reset signal, I'm persuaded these problems would not be an issue. For some reason, Intel liked positive-going reset and interrupts, which made them more costly and cumbersome to apply. For that reason, I, personally, have used Intel parts very seldom.

I used there 8287 to correct a layout error rather than respinning a board. I did use 8748-family parts a few times, and I used COTS (Multibus) Intel-MCU boards from time to time (seldom, as they were costly) for industrial applications. I did like, very much, to use their i80186 CPU, though.

Using Vdd-based reset always seemed silly to me, as Vcc wanders around quite a bit, even under normal circumstances. Vss, OTOH, remains quite well-defined throughout power-up and power-down.

Average designers often use a somewhat too-weak PSU, and compensate for the weak PSU by adding lots of Vdd-Vss capacitance. This makes the rise and, espacially, the fall-time of Vdd slow, as things stop draining the Vdd supply. I've had cases in which an all-CMOS circuit was in the mail for two weeks and ultimately returned, and even though it had only a 4.7 uF cap on Vdd, the clock/calendar was still very much in sync with the rest of the world, despite the fact no battery had been installed yet. More common, however, is the decay of Vdd taking multiple tens of seconds before it is below the level at which components can run. It's for that reason that I focus on the decay of Vdd when considering the flash-corruption issue.

I'm not sure why things continue after RESET is asserted. I'm not sure that this happens on all, or even many different MCU's, but I have seen it on several, albeit in the same physical circuit, and it was not FLASH but, rather, BBRAM that was routinely corrupted.

Clearly, this needs further examination.

I really do wish there were more 805x-core-specific information regarding rise and fall of Vdd. That's where I believe the gremlin lives.

RE