The SPI protocol isn't really necessary in this case. There are many devices, e.g. 74HC595

Going back to the beginning, the O/P wishes to drive a matrix of relays configured as a rows and 8 columns (I think) using 8 (source) high-side drivers (UDN2982) and 8 (sink) low-side drivers (ULN2803). In order to produce a persistent control signal, he must have a memory element of some sort in the mix. I proposed that he use a 74HC107 configured as a "T" flipflop for each relay. Any flipflop configured as a "T" flipflop would work, of course. After some consideration, I concluded that any serial-in-parallel-out shift register would work just as well to drive either the source or the sink. However, I'm puzzled with why he wants to drive both the source and the sink, i.e. why he can't just drive either the sources or the sinks. I'm also puzzled by the question of why he won't tell us how he expects to use only eight of each driver, to manage this task.

It's been stated repeatedly that relays are much slower than the MCU. I'm not sure that the O/P has ever examined a specification for relays. Perhaps, after the repeated exhortation to do so, he has. There are ways, I suppose, of constructing a matrix that might operate latching relays on a push-on/push-off basis. That's one way of routing controls. It doesn't explain why the O/P has "issues" with the ULN/UDN question.

It's time the O/P explains himself.

RE