Maximum transition time of input signal is about 500nsec for 74HCMOS (Vcc = 5V) and about 4µsec for CD4000 (Vcc=15V). The transition time is defined as the time needed to swing from 10% to 90% of signal, which is 0.5V and 4.5V for a 5V signal.
The reason that input signal must not have higher transition times under normal operation is the internal feedback from output to input of a gate. If you slowly rise the input signal to about 50% of Vcc for a CMOS gate, then you come to a region, where the output of gate toggles. This will result in a feedback to input circuitry of gate, which wants to make the output to toggle not only one time, but repeated times, because only a small noise (here charge injection from the output signal toggle) is needed to make the output to toggle repeatedly.
The maximum allowed transition time depends on the time the input signals needs to traverse this critical threshold region and depends on the amount of internal feedback. It's clear that when the output transition time is very short, because you have a fast gate, that the internal feedback is stronger and that only a rather short input transition time is allowed.

While for a standard gate this threshold region is about 10mA...100mV, a Schmitt-trigger input can have a threshold region of several volts. So, it's nearly impossible to make a gate producing more than only one output toggle, when the input signal rises or falls very slowly.


It's very difficult to give a complete list of all design techniques here. Please have a look at the "8052 FAQs" on the left.

Kai