Having gone through the link given by you, i understood the schmitt trigger based debounce circuit resonably well.
Thank you.
Its wonderful to see the facts being proved beautifully with the description of scope plots.


i saw the data sheet of 7400 for any transition time given for its i/p. couldnt find anything like that.
Also, i couldnt think out how a delay in a 0 - 5 V transition at a NAND gate i/p could affect its o/p - 'in what ways'.
can you give me some hints on understanding the increased transition time phenomena that would affect the gate o/p's?(when using a NAND gate or in general).


also previously you have said...

These unwanted spikes can come from ESD events or from noise being injected into the trigger input by unavoidable stray capacitance.

and i think, there are also many other factors that could be responsible for noise in electronics circuits.

So, if possible can i have your comments on the filtering techniques that could be handled to overcome (or)
control these noise related issues, thereby enhancing the life of the product being made.

In short, 'i would like to know how the noise related issues should be handled when designing a new product'.

your suggestions could be highly helpful.

Thanking you,
suresh.