??? 03/02/06 03:14 Read: times |
#111025 - Analysis Responding to: ???'s previous message |
Suresh said:
The 10k and 1uF forms a differentiator network which delivers positive and negative going spikes.
The diode is used to limit the amplitude (by becoming frwd biased) at trigger i/p to .7V during the positive going spike. Exactly! It's to prevent damage from TLC555. Suresh said:
This .7V flow to the RC network 1K / 10nF.( - Kindly give me few info to know the use of this RC network) This RC ntework forms a low pass filter to suppress unwanted voltage spikes from eroneously triggering the monoflop. These unwanted spikes can come from ESD events or from noise being injected into the trigger input by unavoidable stray capacitance. This, especially, if the switch is mounted in some distance to the circuit, or if you don't put the circuit into a metalic enclosure (Faraday cage). Suresh said:
The reset pin is also connected with a similar difftr network with voltage limiting diode. Here the reset pin receives .7V (typical value for device reset when current through it is .1mA) Although looking very similar, the function is different: Whenever you turn-on the supply voltage of monoflop, the TLC555 will deliver an unwanted pulse at output of about the adjusted period, even if the switch wasn't pressed at all. Happily, the TLC555 provides a reset input, which allows you to suppress this first pulse. This is done by feeding the supply voltage via a RC-network to the reset pin: Immediately after turn-on of supply voltage, reset pin sees logic low level, which resets the monoflop. No first pulse will occur. When the 10µF cap is charged, on the other hand, reset pin becomes deactivated and the monoflop is ready to wait for the switch to be pressed. The diode across 220k resistor is needed to speed-up the discharge of 10µF cap again, when the supply voltage is turned-off. This fast discharge is supported by the 1k resistor at V+ terminal. Suresh said:
Lastly regarding that transistor Bc550,
i could only find that it will be 'ON' for the time delay i will be setting with the Pot. ...i am unable to come to a conclusion on how it rectifies the problem of abnormality. Have a look at figure 4 of http://www.fairchildsemi.com/ds/NE%2FNE555.pdf again, to see what condition must be met, to cause abnormal triggering: It's a logic low level at trigger input (pin2 of TLC555) at the end of monoflop pulse, before the monoflop pulse was ended! The BC550 now shorts the switch input to ground immediately after the switch was pressed. This forces the trigger input (pin2 of TLC555) to logic high level during the whole monoflop pulse (at least, after the 1µF cap was charged by the second 10k resistor, which took only about 10k*1µsec = 0.01sec). So, no abnormal triggering can occur. Kai |