i analysed the circuit for trigger i/p considering the NAND gate operation alone.

what i got is,
the NAND gate connected to the switch:
initially both of its i/p are high. So, the low o/p of this gate leads to the two i/p's (one is inverted with 1mSec delay) of the NAND gate connected to the trigger. so the trigger i/p is high when the switch is not pressed.

When the switch is pressed:
A low going spike is applied to NAND i/p by pressing the switch, So a high to low spike is obtained in the trigger i/p since, both the i/p of the NAND gate connected to the Trigger i/p will be high for 1mSec (RC network is used for this).
After which the feedback NAND gate takes control and maintains the trigger i/p high.
once the o/p pulse is over, this feedback NAND o/p goes high again. In this case when the switch is released (after the set delay elapses) the voltage level at trigger i/p may not change due to the NAND gate connected to its i/p (with one i/p inverted).

did i got it right?

However iam not clear of what a NAND gate does with a Schmitt trigger operation in it?

Thanking you,
suresh.