| ??? 01/08/10 16:27 Read: times |
#172269 - micro-SD might be the answer Responding to: ???'s previous message |
Jan Waclawek said:
Richard Erlacher said:
... at least not from the standpoint of complicating the write process. Wear leveling isn't an issue until you start to write to a specific sector thousands of times. True. It's just a secondary issue. The primary is ECC. Richard Erlacher said:
I think the O/P wants to buy and use bare NAND Flash chips. If he wants to generate address space for 2 GB, he'll have to work a bit, as 2GB requires 31 addresses. Some demultiplexing scheme is obviously indicated. This is not the case. The standard NAND's "address bus" is already multiplexed. I mentioned ONFI, where the standards can be found; but it's enough to look into any NAND's datasheet. The 17 pins should be enough for any NAND. Some may require a large RAM buffer, though. While it doesn't require 31 i/o's it does require management of 31 addresses. This consumes time and resources. Even 17 I/O's will be somewhat burdensome for any 805x implementation, particularly since the O/P probably wants to exploit some of the "features" of the MCU he's chosen, which are bound to certain pins. Using an SD card, he'll save money (I recently bought a couple of 2GB micro-SD cards with SD adapter for my cameras for $3 per each plus postage), as opposed to buying the NAND chips at a small (less than 100k units per week) scale, and he can eliminate most of the hardware overhead, having reduced his interface complexity to protocol rather than external logic. I would be concerned about using that high capacity chip though. I don't know where exactly is nowadays the boundary between SLC and MLC (i.e. those which store one versus more bits per transistor, respectively), but MLC require more thoughtful ECC than SLC.
Richard Erlacher said:
If, however, he wants to use SD/MMC, particularly in SPI mode, he'll have a much easier time, since fewer I/O's are required. Moreover, there are published software solutions for the SPI approach with MMC ... solutions which are purportedly easy to apply to SD. Agree. This is why I posted the link to the thread where we already discussed this issue. JW Unfortunately, we don't know what objective the O/P had in mind, so it's hard to assess where the specific advantages of various technologies are. If he expects any sort of bandwidth demand, he'll have to implement his own wear-leveling approach, else his chips will "wear out" eventually. RE |
