| ??? 01/08/10 16:07 Read: times |
#172266 - wear leveling and address lines Responding to: ???'s previous message |
Richard Erlacher said:
... at least not from the standpoint of complicating the write process. Wear leveling isn't an issue until you start to write to a specific sector thousands of times. True. It's just a secondary issue. The primary is ECC. Richard Erlacher said:
I think the O/P wants to buy and use bare NAND Flash chips. If he wants to generate address space for 2 GB, he'll have to work a bit, as 2GB requires 31 addresses. Some demultiplexing scheme is obviously indicated. This is not the case. The standard NAND's "address bus" is already multiplexed. I mentioned ONFI, where the standards can be found; but it's enough to look into any NAND's datasheet. The 17 pins should be enough for any NAND. Some may require a large RAM buffer, though. I would be concerned about using that high capacity chip though. I don't know where exactly is nowadays the boundary between SLC and MLC (i.e. those which store one versus more bits per transistor, respectively), but MLC require more thoughtful ECC than SLC. Richard Erlacher said:
If, however, he wants to use SD/MMC, particularly in SPI mode, he'll have a much easier time, since fewer I/O's are required. Moreover, there are published software solutions for the SPI approach with MMC ... solutions which are purportedly easy to apply to SD. Agree. This is why I posted the link to the thread where we already discussed this issue. JW |
