... at least not from the standpoint of complicating the write process. Wear leveling isn't an issue until you start to write to a specific sector thousands of times. The reason that wear leveling is provided in CF, SD, MMC, etc. devices is that people tend to erase their picture cards, MPG and JPG stores and replace them, rather than distributing them over the entire memory space. As a result, the likelihood that one will "wear out" that particular portion of the memory increases. CF/SD/MMC/etc. makers provide an on-board MCU to handle that task. True, it requires time to do those things, just as it requires time to write a sector, but they try to help us with that MCU. If, however, you were to use a CF card as a disk drive for, say, Windows, you'd get maybe two days' life out of the thing, because it probably writes 5000 times per minute during certain processes, e.g. defrag. and who knows how that would impact the Windows OS? When you're copying to a CF from a hard disk, the CF is fast, but what happens when the CF card wants to "wear level"?

I think the O/P wants to buy and use bare NAND Flash chips. If he wants to generate address space for 2 GB, he'll have to work a bit, as 2GB requires 31 addresses. Some demultiplexing scheme is obviously indicated.

If, however, he wants to use SD/MMC, particularly in SPI mode, he'll have a much easier time, since fewer I/O's are required. Moreover, there are published software solutions for the SPI approach with MMC ... solutions which are purportedly easy to apply to SD. The MCU he's wanting to use in no way will tax the performance of SD/MMC devices. I believe it's only if he's in a hurry, which he clearly isn't, based on his choice of MCU, that write delays and wear-leveling would offer a challenge.

RE