| ??? 07/27/09 11:17 Read: times |
#167924 - sure not Responding to: ???'s previous message |
Per Westermark said:
Note that many JTAG solutions are better than just boundary scan. Well, I would not use "better" in this context. It's just the JTAG acronym is so often misused for OCD (on-chip debugging). Per Westermark said:
The big difference between a JTAG interface and using a monitor software is that the JTAG allows single-stepping from the first instruction, and can debug most situtations where the chip locks up. And you can use the full flash size for the application program. The debug block in the processor allows breakpoints in the flash address range, without reprogramming the flash with any magic sw instructions. Yes, if an OCD module is available, it is superior to a shear monitor (and, an most respects, inferior to a real ICE). Apparently, there is no standard-clocking-40-pin OCD '51 derivative around (which is what we're talking about here). I've heard of some SiLabs-chips-based solutions adopted to 40 pins, but the timing is definitively off (plus issues with supply/signal voltages in 5V applications). There appear to be real-ICEs here, though, as said above, but pricey as usual. On the other hand, SoftICE is free (as in free beer - as long as you have Keil's), readily available, and has its limitations. Contrary to the version of FlashMON for Atmel's RD2s, using the fact it resides in the extra bootFlash, almost all of the 64kB application Flash is available for the application (IIRC SoftICE uses one 512byte block of the userFlash), and also the whole ERAM. So, summing up, there's a reasonably good and free core-mode monitor and several true ICEs (pricey) available for the RD2s; OCD and no ICE nor monitor for the AVRs. I would also stress the fact, that all of these are only auxiliary tools to the only real debugger, which sits between the chair and the keyboard. JW |
