In this case, you got quite bad timing.

The cost of doing unaligned access is only a cost when doing accesses larger than one byte. In this case, it doesn't matter if the destination is one, two or three bytes unaligned. The only punishment is that the memory interface is run at a quarter of the maximum speed since the ARM isn't allowed to do 32-bit transfers.

The problem here is that the load will take 3 clock cycles and the store 2 clock cycles for an ARM7 core. The flash is big enough that a $5 chip can do a full unroll of 4k byte transfers and consume no more than 1/8 of the flash (four bytes read instruction, four bytes write instruction - probably two bytes read, two bytes write for same speed if using thumb mode). To do 60ns/transfer, that would then require 12ns cycle time, i.e. 83MHz. The chip I am using can't do more than 72MHz so it fails the 60ns/byte requirement. It would need 77MHz for 65ns/byte.