I use lower-case for bits.

The device to which I often refer is the SMSC 34C80, which once was an EPP "target" interface chip. The mfg touted it being capable of producing a real-time 8 MHz AT-style ISA bus from the EPP channel. This was back in the early '90's, so I have to believe it was from a fast '486, which was the popular machine of the time.

I've never proven this, of course, but I doubt the mfg would maintain the info about it if it were untrue.

EPP is an arrangement whereby the support hardware produces either an address strobe (if the access, read or write is to address <base+3> while it produces a data strobe when the access is to address <base+4..base+7>. This means that the EPP can generate a byte transfer as fast as the system can do it, and it can do it long-word-wise if it's transferring data. The hardware, of course, has to sort out where the data goes, which is not so simple in the case of a long-word, or word, much less an odd number of bytes successively written to the data channel. If you write a 32-bit data word to the data port, the hardware shuffles it out as fast as the target can swallow it, albeit one byte at a time, as the channel width is only a byte. It does no serial communication at all, unless you force it to bit-bang, which it, naturally, must do with considerable software overhead.

Read the spec, if you like.

RE