What's more, it's just a "red herring" ...


What you're tired of, Erik, apparently is reading the datasheet for the SiLabs parts you like to pimp so much.

What part of the 8255 is it that doesn't "match modern technology" as you put it? Is it important to you that the date-codes match?

You've been asked this before, but failed to come up with an answer.

The 2N3904 and 1N914A are old, too, and resistors and capacitors have been around nearly forever ... yet all still work. Do you refuse to use them, too?


That would be better than the nonsensical drivel you've been spouting for the past year or two. If, at least, you'd read the datasheets ... <sigh> ...

Then, what sort of processor WOULD you choose, Erik? The reactors I know of use 'em right and left. 192 outputs is not a big job. It takes only eight 8255's. No matter what sort of processor you use, you still have to provide the I/O. How would YOU do it?

It's easy to say, "It's old, it's slow, it's this, it's that," but coming up with a positive construct is not so easy.

What it amounts to, Erik, is that you're covering up your own ignorance and lack of experience with blanket statements that are just simply false.

Here's a bit from the datasheet of your favorite series, regarding the external memory interface timing,

"The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution time for an off-chip XRAM operation is 5 SYSCLK cycles (1 SYSCLK for /RD or /WR pulse + 4 SYSCLKs).
For multiplexed operations, the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles. Therefore, the minimum execution time for an off-chip XRAM operation in multiplexed mode is 7 SYSCLK cycles (2 for /ALE + 1 for /RD or /WR + 4). The programmable setup and hold times
default to the maximum delay settings after a reset. Table 17.1 lists the ac parameters for the External Memory Interface, and Figure 17.4 through Figure 17.9 show the timing diagrams for the different External Memory Interface modes and MOVX operations."

(have a look at SFR Definition 17.3. EMI0TC: External Memory Timing Control)

This clearly states how you can, if you'll get your head unwedged, demonstrate that the 8255 will work just fine with this "modern technology." Now, as I've often said, the 8255 has limited output current, and that's the reason I've seldom used 'em. It's enough to drive the base of a darlington, though. If you look inside any of a number of nuclear power plants, you'll see there are control outputs that originate in an 8255, in fact, on an Intel board that contains several of them. They work, and, in fact, they work very well. Why would anyone refuse to use technology that works?

RE