??? 10/12/06 22:43 Read: times |
#126356 - battery Responding to: ???'s previous message |
Richard said:
I'm thinking that if I allow the osc-out pin to drive a 2-bit shift-register with an XOR across it, it will produce a 2-cycle long reset pulse, as specified in one or another datasheet. Erik Malund said:
then you better get a separate supply for the logic. How else are you going to guarantee that reset is there when the power supply ramp up. Yes, a battery. The best (and most expensive) reset ICs do use them (although only as a side effect as they provide glitch-free chipselect for battery-backuped SRAMs). Anyway, I wouldn't do that at all. Or, if, I have an oooold idea for a combined reset/wakeup, but I'd need access to IC manufacturing process and a few M$s to make it :-))) JW |