Verilog is more like 'C' while VHDL is syntactically more like ADA. Lots of folks can program in 'C', hence they don't get as much money as the guys who can program in ADA. VHDL was slow getting onto the market, but because it's mostly free, it's not losing market share. It's less popular in the U.S. because more people use Verilog because it's been available in useable form for much longer.

Verilog was written, originally, by guys who understood software tools. VHDL was developed by a team that knew hardware design really well. Verilog was a commercial effort from day-1. VHDL was a government project ... <sigh> ...

Not all those government things are bad, though. I really don't like the ANSI symbols for logic. The ones everybody can comprehend are the U.S. military symbols. Feature that!

The Verilog guys like it, though, and the guys who sell it, make lots of $$$ since it's VERY expensive. They also buy magazine advertisements.

I'll learn Verilog when there's a FREE (as in free beer) Verilog not dedicated to one hardware vendor or another.

They're working in Europe on C++ dialects that splice into VHDL and will integrate/optimize the code such that the compiler generates VHDL code that's optimized for the C++ code to be executed. That's an interesting "next step" don't you think?
You just write your code and compile it into a hardware scheme that contains the ROM, RAM, and I/O that's needed to form an ASIC. I don't know how long it will take, but that's promising at least in concept.

... and, speaking of free beer ... has anybody tried "Fat Tire" from New Belgium Brewing? ...

RE