I haven't found a decent enough VHDL version that actually produces JEDEC files suitable for a 16V8 or 20RA10, though.

those of you that get EE Times will have seen the survey that did show that System Verilog and Verilog will have more users next year while VHDL will have fewer.

Anyhow, I think both Verilog and VHDL are far too capable (complicated) for simple PLD programming.

Fot those you have PALASM and ABEL which anyone familiar with Mr. Booles algebra can use after 1/2 hour of familiarization.

Erik