this display uses an interface that allows twice the data rate of the classic HD44780, i.e. it has a 500 ns 'E' clock cycle rather than the much slower (nominally 1 MHz witha 400 ns minimal 'E' pulse width) cycle rate of the classic HD44780.

The required data setup before 'E' is 60 ns, and RS and R/w can be set up at the same time.

I'm persuaded that a small CPLD will do just fine, as it can operate from the MCU clock at the "A" end and transmit the 13 bits (start, DQ(7..0), RS, R/w, parity, stop). The stop cycle can be used as a cycle to decide whether to return an ACK pulse. The data is registered in the CPLD at the "A" end, so it can be retransmitted if the ACK doesn't arrive within 2 clock cycles. It would work like a number of other minimal comm schemes such as the IBM keyboard signaling protocol. Since the CPLD can produce differential signaling without external buffers, that should work just fine, though it can also operate like the PC keyboard, which is single-ended. With e volts, I'd be inclined to operate with differential signaling. 20 meters is not unrealistic at nominally 1 MHz. With "good" cabling, higher signaling rates could be achieved. IIRC, the IBM PC keyboard used a considerably higher rate, though it only worked over a meter and a half.

With a 1 MHz driver clock the CPLD can perform the setup and then achieve the transfer. Things get "interesting," however, if the "A" board monitors the busy flag, as it probably should. In such a case, the hardware has to "know" that it should ignore reads.

RE