The work i've done seems to indicate that a Fast Micro is required as much or more for timing "granularity" as for a rapid "code path".

The limitation to driving a VGA monitor is the pixel rate at ~25MHz.

Using an external shift register clocked at the pixel rate and derived from the micro clk (to ensure synchronous loading) this issue is moot for timing.

Even at twice the H-sync rate the DS'4x0 platform could drive a 640x480 display.

If you would allow an additional chip then you could deploy a 54ACT715 (or small FPGA) to generate both V/Hsync/Blanking and now the micro only need satisfy the shift register.

regards,
p