| ??? 07/24/12 20:42 Read: times |
#187971 - contraints Responding to: ???'s previous message |
Mahmood Elnasser said:
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
However when I implement design again it disappears. The project works fine is this an issue in my design or is it the tool? Mahmood Are the timing constraints real? This means: you have to have a timing constraint for the clock that's the input to the DCM. The tools will figure out what the constraints for the DCM outputs should be. Did you make any changes in the source between runs? -a |
| Topic | Author | Date |
| VHDL DCM problem | 01/01/70 00:00 | |
| coregen | 01/01/70 00:00 | |
| Example found in tool itself! | 01/01/70 00:00 | |
| Xilinx DCM | 01/01/70 00:00 | |
| BUFG | 01/01/70 00:00 | |
| re: BUFG | 01/01/70 00:00 | |
| Can you share it? | 01/01/70 00:00 | |
| Basically don't use coregen | 01/01/70 00:00 | |
| Altera and Xilinx , probably lattice soon | 01/01/70 00:00 | |
| Altera joy | 01/01/70 00:00 | |
| USB blaster clones | 01/01/70 00:00 | |
| it's working!!!! | 01/01/70 00:00 | |
| this warning... | 01/01/70 00:00 | |
| I don't know | 01/01/70 00:00 | |
| new warning | 01/01/70 00:00 | |
| contraints | 01/01/70 00:00 | |
| No change to source | 01/01/70 00:00 | |
Timing Constraints | 01/01/70 00:00 | |
| CoreGen FTL | 01/01/70 00:00 |