| ??? 07/13/12 14:40 Modified: 07/13/12 15:02 Read: times |
#187925 - Basically don't use coregen Responding to: ???'s previous message |
Unless you really have to because it is very buggy.
I have spent this last week replacing all of the coregen stuff in a design with code which directly infers all the components. The latest exciting bug to hit coregen is one where the xilinx ide crashes for whatever reason, but as it is crashing it manages to write to your project files, corrupting them. Inferring stuff with behavioural code is the way to go. Oh and having messed with xilinx latest version , much prefer altera at the moment, at least they still support modelsim. |
| Topic | Author | Date |
| VHDL DCM problem | 01/01/70 00:00 | |
| coregen | 01/01/70 00:00 | |
| Example found in tool itself! | 01/01/70 00:00 | |
| Xilinx DCM | 01/01/70 00:00 | |
| BUFG | 01/01/70 00:00 | |
| re: BUFG | 01/01/70 00:00 | |
| Can you share it? | 01/01/70 00:00 | |
| Basically don't use coregen | 01/01/70 00:00 | |
| Altera and Xilinx , probably lattice soon | 01/01/70 00:00 | |
| Altera joy | 01/01/70 00:00 | |
| USB blaster clones | 01/01/70 00:00 | |
| it's working!!!! | 01/01/70 00:00 | |
| this warning... | 01/01/70 00:00 | |
| I don't know | 01/01/70 00:00 | |
| new warning | 01/01/70 00:00 | |
| contraints | 01/01/70 00:00 | |
| No change to source | 01/01/70 00:00 | |
Timing Constraints | 01/01/70 00:00 | |
| CoreGen FTL | 01/01/70 00:00 |