After doing Xilinx for a million years, I no longer use the Core Generator. But for setting up DCMs, it actually helps. Of course, now I have a template, and I tend to put an entity called clocks.vhdl in all of my designs; that entity is where all clocks are derived and it neatly wraps up the DCMs and the associated buffers.

The important thing to remember is that XST is really kinda stupid, and you have to instantiate the BUFGs for all of the DCM inputs and outputs.

So, at minimum, you need a BUFG for the input clock (which drives the DCM CLKIN) and a BUFG for each output. So if you use CLK0, CLK2X and CLKFX, you need three more BUFGs. In addition, the output of the CLK0 BUFG should be used to drive the CLKFB input (and set the generic that indicates clock feedback 1X or 2X to 1X).

And it gets worse: ISE is too stupid to correctly place the location of the buffers. You'll get a dire warning about how the BUFGMUX (which is really what you get when you instantiate a BUFG) is placed on the other side of the FPGA, precluding using the fast clock path from the clock input pin. Yes, the tools put the BUFGMUX on the wrong side of the chip, even though the documentation makes quite clear which BUFGMUX is associated with which GCLK input pin and which DCM. So, at minimum, you'll have to LOC the BUFGMUX connected to the input pin.

Good luck!

-a